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| author | Nathan Bossart <nathan@postgresql.org> | 2025-01-10 13:18:04 -0600 |
|---|---|---|
| committer | Nathan Bossart <nathan@postgresql.org> | 2025-01-10 13:18:04 -0600 |
| commit | 3d0b4b1068018f624d5ef7c9f90b536ed58345b5 (patch) | |
| tree | d6a07feca10bd4a18d18363204e33309ba8f8b6e /src | |
| parent | 28e7a9968e183a6b8dddaff5b513b0656ba349aa (diff) | |
| download | postgresql-3d0b4b1068018f624d5ef7c9f90b536ed58345b5.tar.gz postgresql-3d0b4b1068018f624d5ef7c9f90b536ed58345b5.zip | |
Use a non-locking initial test in TAS_SPIN on AArch64.
Our testing showed that this is helpful at sufficiently high
contention levels and doesn't hurt performance on smaller machines.
The new TAS_SPIN macro for AArch64 is identical to the ones added
for PPC and x86_64 (see commits bc2a050d40 and b03d196be0).
Reported-by: Salvatore Dipietro
Reviewed-by: Jingtang Zhang, Andres Freund
Tested-by: Tom Lane
Discussion: https://postgr.es/m/ZxgDEb_VpWyNZKB_%40nathan
Diffstat (limited to 'src')
| -rw-r--r-- | src/include/storage/s_lock.h | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/src/include/storage/s_lock.h b/src/include/storage/s_lock.h index 516fffc53ab..2f73f9fcf57 100644 --- a/src/include/storage/s_lock.h +++ b/src/include/storage/s_lock.h @@ -263,18 +263,24 @@ tas(volatile slock_t *lock) #define S_UNLOCK(lock) __sync_lock_release(lock) +#if defined(__aarch64__) + /* - * Using an ISB instruction to delay in spinlock loops appears beneficial on - * high-core-count ARM64 processors. It seems mostly a wash for smaller gear, - * and ISB doesn't exist at all on pre-v7 ARM chips. + * On ARM64, it's a win to use a non-locking test before the TAS proper. It + * may be a win on 32-bit ARM, too, but nobody's tested it yet. */ -#if defined(__aarch64__) +#define TAS_SPIN(lock) (*(lock) ? 1 : TAS(lock)) #define SPIN_DELAY() spin_delay() static __inline__ void spin_delay(void) { + /* + * Using an ISB instruction to delay in spinlock loops appears beneficial + * on high-core-count ARM64 processors. It seems mostly a wash for smaller + * gear, and ISB doesn't exist at all on pre-v7 ARM chips. + */ __asm__ __volatile__( " isb; \n"); } |