diff options
Diffstat (limited to 'src/include')
| -rw-r--r-- | src/include/pg_config.h.in | 6 | ||||
| -rw-r--r-- | src/include/port/atomics.h | 2 | ||||
| -rw-r--r-- | src/include/port/atomics/arch-ia64.h | 2 | ||||
| -rw-r--r-- | src/include/port/atomics/fallback.h | 4 | ||||
| -rw-r--r-- | src/include/port/atomics/generic-acc.h | 106 | ||||
| -rw-r--r-- | src/include/port/hpux.h | 3 | ||||
| -rw-r--r-- | src/include/storage/s_lock.h | 105 |
7 files changed, 40 insertions, 188 deletions
diff --git a/src/include/pg_config.h.in b/src/include/pg_config.h.in index cdd742cb55b..7133c3dc66b 100644 --- a/src/include/pg_config.h.in +++ b/src/include/pg_config.h.in @@ -430,9 +430,6 @@ /* Define to 1 if you have the `pread' function. */ #undef HAVE_PREAD -/* Define to 1 if you have the `pstat' function. */ -#undef HAVE_PSTAT - /* Define to 1 if the PS_STRINGS thing exists. */ #undef HAVE_PS_STRINGS @@ -625,9 +622,6 @@ /* Define to 1 if you have the <sys/procctl.h> header file. */ #undef HAVE_SYS_PROCCTL_H -/* Define to 1 if you have the <sys/pstat.h> header file. */ -#undef HAVE_SYS_PSTAT_H - /* Define to 1 if you have the <sys/resource.h> header file. */ #undef HAVE_SYS_RESOURCE_H diff --git a/src/include/port/atomics.h b/src/include/port/atomics.h index 9550e04aaa5..33b7fd6042c 100644 --- a/src/include/port/atomics.h +++ b/src/include/port/atomics.h @@ -95,8 +95,6 @@ #include "port/atomics/generic-gcc.h" #elif defined(_MSC_VER) #include "port/atomics/generic-msvc.h" -#elif defined(__hpux) && defined(__ia64) && !defined(__GNUC__) -#include "port/atomics/generic-acc.h" #elif defined(__SUNPRO_C) && !defined(__GNUC__) #include "port/atomics/generic-sunpro.h" #else diff --git a/src/include/port/atomics/arch-ia64.h b/src/include/port/atomics/arch-ia64.h index 771bac1f3ee..264d2316b97 100644 --- a/src/include/port/atomics/arch-ia64.h +++ b/src/include/port/atomics/arch-ia64.h @@ -21,8 +21,6 @@ # define pg_memory_barrier_impl() __mf() #elif defined(__GNUC__) # define pg_memory_barrier_impl() __asm__ __volatile__ ("mf" : : : "memory") -#elif defined(__hpux) -# define pg_memory_barrier_impl() _Asm_mf() #endif /* per architecture manual doubleword accesses have single copy atomicity */ diff --git a/src/include/port/atomics/fallback.h b/src/include/port/atomics/fallback.h index 1cdef5f2f6f..91a9be48288 100644 --- a/src/include/port/atomics/fallback.h +++ b/src/include/port/atomics/fallback.h @@ -93,7 +93,7 @@ typedef struct pg_atomic_flag typedef struct pg_atomic_uint32 { /* Check pg_atomic_flag's definition above for an explanation */ -#if defined(__hppa) || defined(__hppa__) /* HP PA-RISC, GCC and HP compilers */ +#if defined(__hppa) || defined(__hppa__) /* HP PA-RISC */ int sema[4]; #else int sema; @@ -111,7 +111,7 @@ typedef struct pg_atomic_uint32 typedef struct pg_atomic_uint64 { /* Check pg_atomic_flag's definition above for an explanation */ -#if defined(__hppa) || defined(__hppa__) /* HP PA-RISC, GCC and HP compilers */ +#if defined(__hppa) || defined(__hppa__) /* HP PA-RISC */ int sema[4]; #else int sema; diff --git a/src/include/port/atomics/generic-acc.h b/src/include/port/atomics/generic-acc.h deleted file mode 100644 index 842b2dec6ed..00000000000 --- a/src/include/port/atomics/generic-acc.h +++ /dev/null @@ -1,106 +0,0 @@ -/*------------------------------------------------------------------------- - * - * generic-acc.h - * Atomic operations support when using HPs acc on HPUX - * - * Portions Copyright (c) 1996-2022, PostgreSQL Global Development Group - * Portions Copyright (c) 1994, Regents of the University of California - * - * NOTES: - * - * Documentation: - * * inline assembly for Itanium-based HP-UX: - * http://h21007.www2.hp.com/portal/download/files/unprot/Itanium/inline_assem_ERS.pdf - * * Implementing Spinlocks on the Intel (R) Itanium (R) Architecture and PA-RISC - * http://h21007.www2.hp.com/portal/download/files/unprot/itanium/spinlocks.pdf - * - * Itanium only supports a small set of numbers (6, -8, -4, -1, 1, 4, 8, 16) - * for atomic add/sub, so we just implement everything but compare_exchange - * via the compare_exchange fallbacks in atomics/generic.h. - * - * src/include/port/atomics/generic-acc.h - * - * ------------------------------------------------------------------------- - */ - -#include <machine/sys/inline.h> - -#define pg_compiler_barrier_impl() _Asm_sched_fence() - -#if defined(HAVE_ATOMICS) - -/* IA64 always has 32/64 bit atomics */ - -#define PG_HAVE_ATOMIC_U32_SUPPORT -typedef struct pg_atomic_uint32 -{ - volatile uint32 value; -} pg_atomic_uint32; - -#define PG_HAVE_ATOMIC_U64_SUPPORT -typedef struct pg_atomic_uint64 -{ - /* - * Alignment is guaranteed to be 64bit. Search for "Well-behaved - * application restrictions" => "Data alignment and data sharing" on HP's - * website. Unfortunately the URL doesn't seem to stable enough to - * include. - */ - volatile uint64 value; -} pg_atomic_uint64; - - -#define MINOR_FENCE (_Asm_fence) (_UP_CALL_FENCE | _UP_SYS_FENCE | \ - _DOWN_CALL_FENCE | _DOWN_SYS_FENCE ) - -#define PG_HAVE_ATOMIC_COMPARE_EXCHANGE_U32 -static inline bool -pg_atomic_compare_exchange_u32_impl(volatile pg_atomic_uint32 *ptr, - uint32 *expected, uint32 newval) -{ - bool ret; - uint32 current; - - _Asm_mov_to_ar(_AREG_CCV, *expected, MINOR_FENCE); - /* - * We want a barrier, not just release/acquire semantics. - */ - _Asm_mf(); - /* - * Notes: - * _DOWN_MEM_FENCE | _UP_MEM_FENCE prevents reordering by the compiler - */ - current = _Asm_cmpxchg(_SZ_W, /* word */ - _SEM_REL, - &ptr->value, - newval, _LDHINT_NONE, - _DOWN_MEM_FENCE | _UP_MEM_FENCE); - ret = current == *expected; - *expected = current; - return ret; -} - - -#define PG_HAVE_ATOMIC_COMPARE_EXCHANGE_U64 -static inline bool -pg_atomic_compare_exchange_u64_impl(volatile pg_atomic_uint64 *ptr, - uint64 *expected, uint64 newval) -{ - bool ret; - uint64 current; - - _Asm_mov_to_ar(_AREG_CCV, *expected, MINOR_FENCE); - _Asm_mf(); - current = _Asm_cmpxchg(_SZ_D, /* doubleword */ - _SEM_REL, - &ptr->value, - newval, _LDHINT_NONE, - _DOWN_MEM_FENCE | _UP_MEM_FENCE); - ret = current == *expected; - *expected = current; - return ret; -} - -#undef MINOR_FENCE - -#endif /* defined(HAVE_ATOMICS) */ diff --git a/src/include/port/hpux.h b/src/include/port/hpux.h deleted file mode 100644 index 4d1dcea70c8..00000000000 --- a/src/include/port/hpux.h +++ /dev/null @@ -1,3 +0,0 @@ -/* src/include/port/hpux.h */ - -/* nothing needed */ diff --git a/src/include/storage/s_lock.h b/src/include/storage/s_lock.h index 98b4d718d29..1e1eb324b43 100644 --- a/src/include/storage/s_lock.h +++ b/src/include/storage/s_lock.h @@ -765,44 +765,14 @@ tas(volatile slock_t *lock) typedef unsigned char slock_t; #endif -/* - * Default implementation of S_UNLOCK() for gcc/icc. - * - * Note that this implementation is unsafe for any platform that can reorder - * a memory access (either load or store) after a following store. That - * happens not to be possible on x86 and most legacy architectures (some are - * single-processor!), but many modern systems have weaker memory ordering. - * Those that do must define their own version of S_UNLOCK() rather than - * relying on this one. - */ -#if !defined(S_UNLOCK) -#define S_UNLOCK(lock) \ - do { __asm__ __volatile__("" : : : "memory"); *(lock) = 0; } while (0) -#endif - -#endif /* defined(__GNUC__) || defined(__INTEL_COMPILER) */ - - -/* - * --------------------------------------------------------------------- - * Platforms that use non-gcc inline assembly: - * --------------------------------------------------------------------- - */ - -#if !defined(HAS_TEST_AND_SET) /* We didn't trigger above, let's try here */ - - -#if defined(__hppa) || defined(__hppa__) /* HP PA-RISC, GCC and HP compilers */ +#if defined(__hppa) || defined(__hppa__) /* HP PA-RISC */ /* * HP's PA-RISC * - * See src/backend/port/hpux/tas.c.template for details about LDCWX. Because - * LDCWX requires a 16-byte-aligned address, we declare slock_t as a 16-byte - * struct. The active word in the struct is whichever has the aligned address; - * the other three words just sit at -1. - * - * When using gcc, we can inline the required assembly code. + * Because LDCWX requires a 16-byte-aligned address, we declare slock_t as a + * 16-byte struct. The active word in the struct is whichever has the aligned + * address; the other three words just sit at -1. */ #define HAS_TEST_AND_SET @@ -813,14 +783,27 @@ typedef struct #define TAS_ACTIVE_WORD(lock) ((volatile int *) (((uintptr_t) (lock) + 15) & ~15)) -#if defined(__GNUC__) - static __inline__ int tas(volatile slock_t *lock) { volatile int *lockword = TAS_ACTIVE_WORD(lock); register int lockval; + /* + * The LDCWX instruction atomically clears the target word and + * returns the previous value. Hence, if the instruction returns + * 0, someone else has already acquired the lock before we tested + * it (i.e., we have failed). + * + * Notice that this means that we actually clear the word to set + * the lock and set the word to clear the lock. This is the + * opposite behavior from the SPARC LDSTUB instruction. For some + * reason everything that H-P does is rather baroque... + * + * For details about the LDCWX instruction, see the "Precision + * Architecture and Instruction Reference Manual" (09740-90014 of June + * 1987), p. 5-38. + */ __asm__ __volatile__( " ldcwx 0(0,%2),%0 \n" : "=r"(lockval), "+m"(*lockword) @@ -829,23 +812,12 @@ tas(volatile slock_t *lock) return (lockval == 0); } -/* - * The hppa implementation doesn't follow the rules of this files and provides - * a gcc specific implementation outside of the above defined(__GNUC__). It - * does so to avoid duplication between the HP compiler and gcc. So undefine - * the generic fallback S_UNLOCK from above. - */ -#ifdef S_UNLOCK -#undef S_UNLOCK -#endif #define S_UNLOCK(lock) \ do { \ __asm__ __volatile__("" : : : "memory"); \ *TAS_ACTIVE_WORD(lock) = -1; \ } while (0) -#endif /* __GNUC__ */ - #define S_INIT_LOCK(lock) \ do { \ volatile slock_t *lock_ = (lock); \ @@ -860,32 +832,31 @@ tas(volatile slock_t *lock) #endif /* __hppa || __hppa__ */ -#if defined(__hpux) && defined(__ia64) && !defined(__GNUC__) /* - * HP-UX on Itanium, non-gcc/icc compiler - * - * We assume that the compiler enforces strict ordering of loads/stores on - * volatile data (see comments on the gcc-version earlier in this file). - * Note that this assumption does *not* hold if you use the - * +Ovolatile=__unordered option on the HP-UX compiler, so don't do that. + * Default implementation of S_UNLOCK() for gcc/icc. * - * See also Implementing Spinlocks on the Intel Itanium Architecture and - * PA-RISC, by Tor Ekqvist and David Graves, for more information. As of - * this writing, version 1.0 of the manual is available at: - * http://h21007.www2.hp.com/portal/download/files/unprot/itanium/spinlocks.pdf + * Note that this implementation is unsafe for any platform that can reorder + * a memory access (either load or store) after a following store. That + * happens not to be possible on x86 and most legacy architectures (some are + * single-processor!), but many modern systems have weaker memory ordering. + * Those that do must define their own version of S_UNLOCK() rather than + * relying on this one. */ -#define HAS_TEST_AND_SET +#if !defined(S_UNLOCK) +#define S_UNLOCK(lock) \ + do { __asm__ __volatile__("" : : : "memory"); *(lock) = 0; } while (0) +#endif -typedef unsigned int slock_t; +#endif /* defined(__GNUC__) || defined(__INTEL_COMPILER) */ -#include <ia64/sys/inline.h> -#define TAS(lock) _Asm_xchg(_SZ_W, lock, 1, _LDHINT_NONE) -/* On IA64, it's a win to use a non-locking test before the xchg proper */ -#define TAS_SPIN(lock) (*(lock) ? 1 : TAS(lock)) -#define S_UNLOCK(lock) \ - do { _Asm_mf(); (*(lock)) = 0; } while (0) -#endif /* HPUX on IA64, non gcc/icc */ +/* + * --------------------------------------------------------------------- + * Platforms that use non-gcc inline assembly: + * --------------------------------------------------------------------- + */ + +#if !defined(HAS_TEST_AND_SET) /* We didn't trigger above, let's try here */ #if defined(_AIX) /* AIX */ /* |